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RE: With a bit of assistance from here and elsewhere ... I believe I have the answer. ...

I drew up a simple gain stage in LTspice - here:




... and wondered why, with high input signal levels, I was getting very high THD in LTspice.

It would seem that the culprit causing the high THD levels is the use of 2SK369s in the above circuit - this causes the Source voltage to be down at 120mV, if I set R4 so that 6ma passes through each jfet.

With a 250mV peak input signal ... I need to have the 'volume pot' (R3/R15) set so that it passes a signal level which is, say, 50mV peak at max.

An improvement (in the simulation, at least) is to replace the 2SK369s with 2SK170s. These have lower gain - so R1 has to be increased to get the same output signal level - but the Source voltage for the same 6ma current through each jfet, becomes 460mV ... producing a significantly lower THD level.

So thanks for your help.




Edits: 09/05/24

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  • RE: With a bit of assistance from here and elsewhere ... I believe I have the answer. ... - andyr 22:11:22 09/05/24 (0)

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