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Upsamplers, DACs, jitter, shakes and analogue withdrawals, this is it.

Appears to be a frequency-locked loop...

...rather than a phase-locked loop. For his circuit, it appears that the control voltage is proportional to the difference in frequency between ref and VCO, rather than phase as in a normal PLL. So it doesn't appear that phase locking is even occurring. I'm sure there is more to it, especially the initialization condition, but it does appear to avoid some problems with PLLs if this is what he's actually doing.


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