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i2s input?

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Posted on August 15, 2013 at 09:35:37

masterlogic
Audiophile

Posts: 4
Joined: May 12, 2013

Can the Audio Note DAC kits be modified to accept an i2s input (one that is not then converted to SPDIF)?

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brettjm

11:12:40 08/17/13

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brettjm

11:12:40 08/17/13

RE: i2s input?, posted on August 17, 2013 at 11:12:40

brettjm
Audiophile

Posts: 1
Location: Northwest
Joined: August 17, 2013

http://www.pavouk.org/hw/modulardac/en_ad1865i2s.html

It is possible but it will take some doing. I've considered making a daughter board that would take the I2S input and do the necessary shift delay and could be spliced into the AD1865 DAC chip. The trick would be in making it so that no damage was done to the digital board in the event that this implementation was a failure. Adding a socket for the DAC chip would be a benefit.

From the website above:

"The converter has I2S input as usual. It has separate data input for left and right channel and "latch" input, which overrides the data from the internal shift register into its own transmitter. Input data format I2S (aligned to the left), the first is delayed by 13 bits, so that after moving the 18 most significant bits in a register in the transmitter transcribed output. In order to simultaneously play back left and right channels at the same time, the data for the left channel is delayed by 32 bits (the frame length for each channel). The result is that the data for the left and right channel of the transmitter will arrive at the same time and by using a common "latch" signal will override both the output. Because it does not produce a 32-bit shift register, I had two options. Be it built using Xilinx circuit, with which I have no experience, or assemble it from commercially available 8-bit shift-registers. Variant with 8-bit registers train I wanted to avoid. Unfortunately prototype 64-bit register of CMOS CD4517 series proved to be non-functional due to different levels of decision-making logic. So I finally used the flock 74HCT164 circuits that perform the function of a delay of 13 bits and 32-bit data register for the left channel. The result exceeded expectations and the transmitter is functional for signals 192kHz/24bit, which is the frequency of 12.288MHz."

For simplicity I made this schematic using the six 74HCT164 shift registers. The digital board already has a 5v power supply. As you can see there are five pins on which the I2S daughter board would need to splice in to the AD1865 DAC.

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