Re: CS8412 jitter reduction PLL or CLOCK? - BFitz - Tweakers' Asylum

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Re: CS8412 jitter reduction PLL or CLOCK?

In Reply to: Re: CS8412 jitter reduction PLL or CLOCK? posted by Gordon Rankin on May 1, 2003 at 13:56:08:

Hi guys
I built one of these external PLL using a CS8412, and it works well.
Look at the CS8412 data sheet, the jitter attenuation kicks in a fairly high frequency, so it does benefit from using a low jitter clock. The best approach is to use a voltage controlled crystal oscillator, or VCXO, running at 11.2896. The PLL circuit can be as simple as using an exclusive OR chip, there was an example on the crystal site. But remember, the pull on a VCXO is fairly limited, maybe +/- 100 PPM, so the transport clock needs to be withing that range. If not, simply replace it. My approach was to use this new low jitter clock to reclock the most critical timing line into the DAC. This was widely copied after it was published in TAA in 2/96. Back then we used the AD1890, but today I'd use a VCXO or just bring the clock from the transport, the easiest approach of all if you have control over that.
What we found was the digital filter could add jitter as well, so it's best to reduce jitter at the last point possible, right before the Dac. A flip flop works really well for reclocking. YOu can easily get to the 10ps range with this approach.
I never tried a straight clock not synched to the transport clock, But I suppose it could work. I guess you could calculate the repeat frequency of slippage knowing the typical clock mismatch. If I remember somone tried this and said it worked OK.
Bob

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Follow Ups Full Thread

Topic - CS8412 jitter reduction PLL or CLOCK? - Gordon Rankin 11:06:56 05/01/03 (9)

Re: Asynchronous Reclocking - Elso Kwak 13:49:23 05/02/03 (0)

Re: CS8412 jitter reduction PLL or CLOCK? - chiggy 16:22:44 05/01/03 (0)

Re: CS8412 jitter reduction PLL or CLOCK? - Ehien 13:47:47 05/01/03 (6)

Re: CS8412 jitter reduction PLL or CLOCK? - Gordon Rankin 13:56:08 05/01/03 (5)

Re: CS8412 jitter reduction PLL or CLOCK? - Ehien 17:43:23 05/01/03 (0)

Re: CS8412 jitter reduction PLL or CLOCK? - BFitz 16:03:18 05/01/03 (3)

Re: CS8412 jitter reduction PLL or CLOCK? UPDATE - Gordon Rankin 08:26:39 05/02/03 (2)

PLL design - Ehien 09:52:06 05/02/03 (1)

Re: PLL design - PBeyer 03:46:27 05/03/03 (0)

Follow Ups

Re: CS8412 jitter reduction PLL or CLOCK? - BFitz 16:03:18 05/01/03 (3)

Re: CS8412 jitter reduction PLL or CLOCK? UPDATE - Gordon Rankin 08:26:39 05/02/03 (2)

PLL design - Ehien 09:52:06 05/02/03 (1)

Re: PLL design - PBeyer 03:46:27 05/03/03 (0)

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